1. Field of the Invention
The present invention relates to the fabrication of multilayer substrates, and more particularly pertains to the incorporation therein of non-destructive test structures utilized to provide visual and electrical test data to facilitate the ascertainment and assessment of potential electrical interface failures. Furthermore, the invention is directed to the provision of embedded structures in a multilayer substrate, such as employed in chip carrier packaging, so as to facilitate electrical testing for via to via alignment and interface layer alignment, and to enable the testing of conductive interface electrical integrity of multilayer electrical devices.
The invention is further directed to the provision of a novel method for the non-destructive testing of electrical integrity in multilayer devices and substrates, as well as implementing electrical testing for via to via alignment and interface layer alignment in multilayer substrates and electrical semiconductor devices, such as are employed in chip carrier packaging.
During the process for the building-up or fabricating of multilayer ceramic substrates there are produced critical electrical interfaces which exist on each layer and also between adjacent or superimposed layers. These interfaces are typically formed on dielectric layers known as greensheets and constitute vias and electrically conductive patterned features such as lines or mesh planes, each of which may have a capture pad or cap provided on their ends in order to increase the contact area with their respective adjoining electrically conductive circuit element. The alignment of each of these interfaces is extremely critical, especially inasmuch as ever narrower line widths and smaller vias are used to be able to increase the wiring density of an electrical device. Also, at high frequencies above 10 GHz, discontinuities in conductor surface features can degrade the electrical performance of signals. Misaligned conductor interfaces can act as such discontinuities and limit the high frequency performance of multilayer devices. Typical specifications permit no more than one-half the diameter of a via as the misregistration or offset between adjacent layers at any location within a laminate. After adjacent layers are laminated the misregistration is practically impossible to quantify within any laminate, unless slow and expensive x-ray tooling is utilized or more accurately if destructive analyses, such as cross-sectioning, are performed on the laminate. This is a time-consuming procedure and provides information concerning alignment between adjacent layers with regard to only a very small area of the substrate. Similarly, when any substrates are made on a single multilayer laminate the traceability of a substrate or of such type of electrical device, which has been found to be defective due to interlayer misalignment, back to the parent laminate is very difficult when serialization of each substrate on each laminate is not employed. Moreover, inasmuch as the laminate may have been subject to poor alignment of the layers in only one corner or small region thereof, not all parts may be defective, and some may be good. By the same account, a substrate or device which has been cross-sectioned and found to possess a good alignment between layers from the center of the laminate may provide false information since devices formed from the corners of the same laminate will typically be subjected to the greatest degree of misalignment from a layer which is slightly rotated during stack-up or lamination within the laminate.
There are also times during processing of cofired multilayer ceramic substrates when shrinkage mismatches between dielectric and conductor features particularly at line to via connections become distorted. This can produce electrical connections which can cause risks of electrical failure during thermal cycling due to CTE (coefficient of thermal expansion) mismatches between the dielectric and conductor.
In actual practice, proper alignment and complete area overlap at these interlayer interfaces is desired; however in reality, there is frequently encountered layer-to-layer misalignment due to greensheet movement during deposition of metallized features, often as organic based pastes, drying, handling, stacking, among other fabrication steps. Similarly, incomplete paste deposition can result in poor via fill. All of these factors can result in partial interlayer overlap with the potential for thermal expansion driven conductor-to-conductor electrical interface failure. This failure mode can be encountered with ceramic substrates when copper metallization, which has a very high coefficient of thermal expansion compared to most ceramics, is stressed during thermal cycling, fails and causes an electrical open. Severe conductor to via or inter layer via misalignment may also result in electrical shorting between metallized features. Likewise failures can be caused by manufacturing process violation of minimum feature separation requirements which may be required to ensure optimum electrical performance. Presently, there are no simple, reliable tests available for non-destructive detection as spacing violations in laminated parts. High-resistance shorts between metallized features can also influence the electrical performance of a semiconductor or electronic package. Ideally, there should be available a method to quickly and non-destructively determine whether an individual device, such as that resulting from the singulation of a multi-up laminate, has good alignment so as to provide an early screening for these types of defects.
2. Discussion of the Prior Art
Although various devices and methods have been developed in the technology for implementing the testing of the electrical integrity of semiconductor devices, particularly such as those which employ multilayer substrates possessing electrical interfaces, and which have electrical devices arranged on the surfaces thereof, including the testing of via to via alignment and layer interface alignment, these are primarily limited in scope and also fail to provide for the desirable kinds of non-destructive testing of these substrates and devices. Fulford, Jr. et al. U.S. Pat. No. 5,916,715 pertains to a process utilizing lithographically deposited metallized features in order to determine the layer alignment of these features for a multilayer substrate of a device. Each and every layer of the multilayer device requires multiple metallized features in order to provide a determination as to whether alignment is obtained within a specified range of microns. The testing which is implemented through the intermediary of this process is not employable for thick film alignment assessments inasmuch as it consumes considerable space on every greensheet layer during processing.
Hanson U.S. Pat. No. 5,863,446 describes an electrical arrangement for extracting layer to layer registration, wherein an alignment test feature is employed in an organic laminate for an electrical device. Resistors are positioned at strategic surface locations in order to determine lateral alignment of laser drilled conductive vias, such vias being produced in laminates requiring precise control of laser energy so as not to pierce the resistive layer which will be employed in order to assess the degree of misregistration, and necessitating precise placement of vias. It is difficult to produce laser holes in a fired ceramic substrate, and even more complex to be able to stop at a buried resistive layer and to subsequently metallize this via to a surface pad which can be probed for electrical integrity.
Lee et al. U.S. Pat. No. 5,756,146 discloses a method which permits optical inspection of metal lines in or on a transparent substrate. To the contrary, ceramic substrates, as well as most high performance chip carriers are not transparent and thus neither a laminated or sintered substrate as employed in the present construction would be suitable for the type of inspection testing disclosed in this patent.
Bayer et al. U.S. Pat. No. 5,283,107 relates to a process for producing a multilayer substrate with a prelaminated building block arrangement of wiring units to assemble a complete wiring pattern for each substrate. There is no test capability provided which will enable interlayer, intrablock or interblock alignment to be investigated nor for testing the integrity of adjacent through-vias, wiring traces or I/O (Input/Output) pads with regard to wiring continuity between selected electrically conductive surface elements and internal metallized features.
Zingher U.S. Pat. No. 4,578,279 relates to the inspection of multilayer ceramic circuit modules through the intermediary of electrical inspection of unfired greensheets. However, this does not enable implementation of any alignment test features to quantify alignment of deposited layer metallization on dielectrics or interlayer stacking alignment.
McMahon U.S. Pat. No. 4,441,075 provides for a circuit arrangement enabling the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips without any physical disconnection. However, there is no capability of providing for non-destructive testing of substrate interlayer shifting, or testing for misalignment or masking offsets relative to the filling of vias analogous in a manner provided for by the present invention.
Accordingly, in order to obviate or ameliorate the drawbacks and limitations of the prior art, applicants have developed a number of test structures which can be employed in order to provide, essentially non-destructively, visual and electrical test data concerning the alignment of electrically conductive and dielectric features which are deposited on multilayer substrates, and which are typically used in chip carrier packaging. These testing features can detect the alignment of metallized features placed on a single layer, as well as provide informative data regarding measureable misalignment of conductive features between layers of a potentiality which can detrimentally impact electrical reliability as well as electrical performance, particularly at very high frequencies where conductive feature-to-feature misalignment may at times produce detrimental signal reflections.
These alignment features can be readily incorporated into pattern deposition masks, such as silk-screening or metal masks employed to deposit conductive features on unfired greensheets using conductive metal pastes. These features can be structured to detect the amount of misalignment that is typically encountered due to mask-layer placement misalignment, greensheet distortion originating from handling, improper placement of via holes used to provide layer to layer electrical interconnectivity, and the like. These alignment features facilitate misalignment detection by means of visual or optical assessment of spacing violations or irregularities between deposited metallized or conductive features.
Applicants further provide inventive test features in the substrate capable of testing the alignment of layer to layer metallized features after the multilayer substrate has been assembled, and in some instances heated to consolidate the assemblage into an electrically functional electronic device, such as a semiconductor chip carrier. The test features allow the assessment of worst case layer misalignment, using surface pads which connect to electrically testable nets able to quantify the degree of (mis)alignment between any two layers, and which can also be used to provide informative data as to which layers of a multilayer laminate or substrate are misaligned.
The information which is acquired from these test features can be utilized to improve electrical manufacturing yields by early detection of conductive feature misalignment which can cause shorts and opens in the manufactured electrical device. The test data can also be used to provide diagnostics of pattern deposition equipment indicative of tooling wear, improper setup or other mechanical malfunctions encountered during production. For high frequency RF applications, typically above 10 GHz, where alignment of layers and features within the package is critical to minimize signal reflections that can adversely affect performance, the test features can be used to confirm the alignment of conductive features and provide monitors during the manufacturing process to quickly indicate potential alignment shifts. These test features would be made as through-via columns (top to bottom) in the substrate to maximize the stress on the via columns and test all the interfaces of the metallization within the substrate. In order to further stress the device, it may be subjected to a very low temperature prior to testing so as to still further stress the interfaces by maximizing the contraction of a metal via column due to CTE mismatch with the dielectric material of the substrate layers. This can be accomplished by immersion in liquid nitrogen or other suitable cryogenic media or methods. Electrical xe2x80x9copensxe2x80x9d testing can be performed during the time the part is maintained at subambient temperatures.
During the subambient temperature or thereafter the xe2x80x9cTop to Bottomxe2x80x9d and xe2x80x9cTop to Topxe2x80x9d connections would be tested for latent opens signatures by known latent defect detection methods. This test structure can be provided for every substrate design and testing can be performed for every substrate. This is necessary since there is typically no traceability to a single laminate after singulation. There is also no simple, accurate non-destructive test available after laminating in order to assess feature to feature alignment.
Accordingly, it is an object of the present invention to provide test structures which will facilitate the obtaining, in non-destructive modes, visual and electrical test data regarding the alignment of electrically conductive and dielectric features which are incorporated within or deposited on multi-layer substrates.
Another object of the invention is to provide test features which can detect and impart informative data regarding measurable misalignment of conductive features on a single substrate layer, as well as intermediate multilayer interfaces of a substrate to ascertain electrical reliability and performance.
A further object resides in the provision of test features to detect the extent of misalignment encountered during mask-layer placement, greensheet or dielectric layer distortion and improper via placement wherein-the test features may be incorporated into pattern deposition masks, such as silk-screening and metal masks.
Yet another object resides in the provision of novel methods employed through the utilization of the test features as described herein in accordance with the invention.